1. Field
The present invention relates to a phase comparator, phase synchronizing circuit, and phase-comparison control method of detecting a phase difference between a reference signal, such as a reference frequency signal, and a referred signal having a desired frequency based on the reference signal.
2. Description of the Related Art
Conventionally, in a phase synchronizing circuit, such as a phase-locked loop (PLL) circuit for use in a wired transmission apparatus, wireless transmission apparatus, general consumer product, and others, for example, a reference signal, such as a reference-frequency signal, is input, thereby generating an output signal that synchronizes with this reference signal and has a desired frequency.
FIG. 6 is a block diagram of a schematic configuration of the inside of a PLL circuit in a conventional technology.
A PLL circuit 100 depicted in FIG. 6 includes a 1/R frequency divider 101 that performs R-frequency-division on a reference signal, a 1/N frequency divider 102 that performs N-frequency-division on a referred signal, which is an output signal of the PLL circuit 100, which will be explained further below, a phase comparator 103 that outputs, based on a phase difference between an R-frequency-divided reference signal φr and an N-frequency-divided referred signal φn, a phase-difference signal for current control so as to decrease the phase difference, a loop filter 104 that outputs a control voltage according to the phase-difference signal, and a voltage control oscillator (VCO) 105 that generates and outputs a referred signal having a desired frequency.
The PLL circuit 100 outputs a referred signal synchronizing with the reference signal according to the phase-difference signal and having a desired frequency.
The phase comparator 103 is assumed to adopt a constant-current charge-pump output phase comparator. Here, the constant-current charge-pump output phase comparator is easy to design compared with a conventional constant-voltage charge-pump output phase comparator due to no dead zone at a locking point where the reference signal φr and the referred signal φn match each other in phase and less errors between simulation and actual measurement values, and also has a small phase noise level and allows operation at high speed.
FIG. 7 is a circuit diagram of a schematic configuration of the inside of the phase comparator 103 according to the conventional technology.
The phase comparator 103 depicted in FIG. 7 includes a phase-difference detecting unit 111 that detects a phase difference between the reference signal φr and the referred signal φn, and a constant-current output unit 112 that produces a charge-pump output of a phase difference signal for current control based on the detection result of the phase-difference detecting unit 111.
The phase-difference detecting unit 111 includes a latch-type flip-flop circuit (hereinafter, simply “D-FF”) for reference signal 111A that detects a rising edge of the reference signal φr, a D-FF 111B for referred signal that detects a rising edge of the referred signal φn, an NAND circuit 111C that resets the D-FF 111A for reference signal and the D-FF 111B for referred signal, and a NOT circuit
The constant-current output unit 112 includes a Complementary Metal Oxide Semiconductor (C-MOS) formed of a P-type field-effect transistor (FET) 112A and an N-type FET 112B, a positive-direction current source 112C, and a negative-direction current source 112D.
For example, as depicted in FIG. 8, when the referred signal φn lags behind the reference signal φr in phase (refer to a timing T1), upon a clock input of a rising edge of the reference signal φr, the D-FF 111A for reference signal inputs a high level (hereinafter, simply “H level”) to the NOT circuit 111D and the NAND circuit 111C.
The NOT circuit 111D inputs to the P-type FET 112A a low level (hereinafter, simply “L level”) according to the H level from the D-FF 111A for reference signal.
The P-type FET 112A brings the source and drain into conduction according to a gate input at an L level, and outputs to the loop filter 104 a phase-difference signal for current discharge from the positive-direction current source 112C.
As a result, when the referred signal φn lags behind the reference signal φr in phase, the phase comparator 103 causes the constant-current output unit 112 to perform a constant-current discharging operation (constant-current output operation) to discharge a current from the positive-direction current source 112C. With this, a control voltage, which is an output from the loop filter 104, is increased. According to the increase in control voltage, the output phase of the referred signal generated and output from the VCO 105 leads.
Furthermore, upon a clock input of a rising edge of the referred signal φn (refer to a timing T2), the D-FF 111B for referred signal inputs an H level to the NAND circuit 111C and the N-type FET 112B.
The NAND circuit 111C produces an inverted input of an L level according to the H level from the D-FF 111A for reference signal and the H level from the D-FF 111B for referred signal to clear (CLR) inputs of the D-FF 111A for reference signal and the D-FF 111B for referred signal.
The D-FF 111A for reference signal and the D-FF 111B for referred signal each produce a clear input of an H level, thereby resetting its output state. As a result, the P-type FET 112A and the N-type FET 112B become in a high-impedance state in which the source and drain are not conducting. Then, the P-type FET 112A causes the constant-current output unit 112 to stop the constant-current discharging operation (constant-current output operation) to discharge a current from the positive-direction current source 112C (refer to an output at the timing T2).
Also, as depicted in FIG. 8, when the referred signal φn leads the reference signal φr in phase (refer to a timing T3), the D-FF 111B for referred signal produces a clock input of a rising edge of the referred signal φn, and inputs an H level to the NAND circuit 111C and the N-type FET 112B.
The N-type FET 112B brings the source and drain into conduction according to a gate input at an H level, and outputs to the loop filter 104 a phase-difference signal for current intake into the negative-direction current source 112D.
As a result, when the referred signal φn leads the reference signal φr in phase, the phase comparator 103 causes the constant-current output unit 112 to perform a constant-current intake operation (constant-current output operation) to take a current into the negative-direction current source 112D. With this, the control voltage, which is an output from the loop filter 104, is decreased. According to the decrease in control voltage, the output phase of the referred signal generated and output from the VCO 105 lags.
Furthermore, upon a clock input of a rising edge of the reference signal φr (refer to a timing T4), the 111A for reference signal inputs an H level to the NAND circuit 111C.
The NAND circuit 111C produces an inverted input of an L level according to the H level from the D-FF 111B for referred signal and the H level from D-FF 111A for reference signal to clear inputs of the D-FF 111A for reference signal and the D-FF 111B for referred signal.
The D-FF 111A for reference signal and the D-FF 111B for referred signal each produce a clear input of an H level, thereby resetting its output state. As a result, the P-type FET 112A and the N-type FET 112B become in a high-impedance state in which the source and drain are not conducting. Then, the N-type FET 112B causes the constant-current output unit 112 to stop the constant-current intake operation (constant-current output operation) to take a current into the negative-direction current source 112D (refer to a timing T4).
With the phase comparator 103 repeating the constant-current output operations including the constant-current discharging operation with ON driving of the P-type FET 112A and the constant-current intake operation with ON driving of the N-type FET 112B, a phase difference between the reference signal φr and the referred signal φn is eliminated.
However, according to the conventional phase comparator 103, as depicted in FIG. 9, when an input break occurs in the reference signal φr, the D-FF 111B for referred signal produces a gate input at an H level to the N-type FET 112B according to a rising edge of the referred signal φn, continuing a constant-current intake operation to the negative-direction current source 112D until a rising edge of the reference signal φr is detected. For this reason, according to a decrease in control voltage to the VCO 105, a VCO output frequency is significantly shifted from the center value. This may disadvantageously cause an output frequency (control voltage) to stick to a lower limit.
To address this situation, PLL-circuit technologies have been known in which the PLL circuit includes an input-break detection circuit that detects an input break of a reference signal and a circuit that produces a switch-output of a VCO control voltage upon detection of an input break of the reference signal (refer to Japanese Utility-Model Application Laid-open No. 5-68132, Japanese Patent Application Laid-open No. 2002-152042, and Japanese Patent Application Laid-open No. 2006-253869).
However, according to the PLL circuit in the conventional technologies mentioned above, the input-break detection circuit that detects an input break of the reference signal is disposed outside of the phase comparator. This, as a matter of course, increases the circuitry size, and may also increase cost according to an increase in the number of components.